Shift register



April 19, '1960 E. G. CLARK SHIFT REGISTER Filed Dec. 20, 1956 M. .Sk N.Sk Rm Y .L E u o Y v mw m V m .n m o m ma A v m w. O O N O O N ^w D o oo o E W v N v M W LIV f E i." n

Y 2,933,522 Patented Apr. 19, 1960 2,933,622 sHrFr REGISTER Edward GaryClark, Greland, Pa., assignbr to Burroughs Corporation, Detroit, Mich.,a corporation of Michigan Application December 20, 1956, Serial No.629,667

16 Claims. (Cl. 307-885) This invention relates to means for causing onebistable device to assume a stable state corresponding to a stable stateof another bistable device, and more pari to store information in abistable device and, in response to a control signal, to transfer thisinformation toanother bistable device. A shift register is an extensionof this concept to a number of bistable devices for the purpose ofstoring and manipulating binary data. the application of a controlsignal, such as a shift pulse, to such a register, the informationstored in each bistable device may be shifted, or transferred, toanother bistable device in the same register. stored in a register totheleft one place is the equivalent of multiplying the storedinformation by the radix 2, and displacing theinformation stored in aregister to the right one place is the equivalent of dividing the storedinformation by the radix 2.

it has heretofore been necessary to provide shift registers with somemeans for preventing the bistable device of a'given stage fromresponding to the input signal appliedto it by the preceding stagebefore said given stage applies a satisfactory vinput signal to thesucceeding stage.` These means have included delay circuits which areincorporated in the input circuits, or output circuits, of `bistabledevices of each stage of a register.

When delay circuits are used, it is also necessary to limit the Width ofeach shift pulse so that it is less than the Displacing the informationVUpon deiay provided; otherwise, the information stored`in`the registerwill be shifted more than one place to the right, for example, for eachshift pulse applied to the register.

The shift register described and claimed herein uses conditionalsteering gates such as are described' and claimed in my co-pendingapplication entitled Conlplemeuting Flip-Flops, Serial No. 629,570,tiled December 20, 1956. Each such gate has two conditions, an enabledcondition and a disabled condition. The condition of a gate, in theabsence of a shift pulse, is determined by the potential of the inputterminal of the bistable device to which the gate has a D.C. connection,A disabled gate will produce substantially Vno output signal when ashift pulse is applied to it. Only when a gate changes from its enabledcondition to its disabled condition upon the application of a shiftpulse, does the gate produce a signal which, if applied to an inputterminal of a bistable device, will cause the device to assume the statecorresponding to, or depending on, the terminal to which the signal isapplied. Conditional steering gates also include means which maintainthem in their disabled conditions while a shift pulse is applied, sothata controlled gates.

change of state of the controlling flip-flop while a shift pulse ispresent has no effect on the condition of the Thus there is no need toincorporate delay circuits in a shift register having conditionalsteering gates.

There is also no'need tolimit the width of each shift pulse since theperiod during which -a bistable device has no control over the steeringgates normally controlled by it is determined by the width of Veachshift pulse. Shift Y registers having conditional steering gates, astaught here-V in, will operate with shift pulses, the Widths of whichmay be of an indefinite duration; i.e., a change in D.C. level. Sincethere vare no fixed time delays incorporated in a shift register havingconditional steering gates and since there is no need to limit thelwidth of each shift pulse, the maximum operating frequency of such ashift register is generally greater than that of a shift register havingdelay means incorporated therein. Also such a shift registeris-easierand more'economical to construct because of the fewer Vand lesscostly components required.

it is, therefore, an object of this invention to provide improved meansfor causing one bistable device to assume a stable state correspondingto a stable state of another bistable device.v

It is a further object of this invention to provideA a shift registerhaving improved performance characteristics and which is easier and moreeconomical to manufacture.

- a shift register, the maximum operating frequency of which issubstantially independent of thev steering gates. It is still anotherobject of tbds invention to provide a shift register in which the Widthof each shift pulse may be substantially ofany duration of time. v

It is still a further object of this'invention to provide a shiftregister in which lthe Width of each shift pulse in excess of thatnecessary to initiate the operation of the Vregister is not a factor inthe proper operation of the shift register.

Other objects and many of the attendant advantages of this inventionwill be readily appreciated as the same become better understood byreference to the following detailed description when considered inconnection with the accompanying drawing, wherein:

Fig. 1 is a schematic diagram of a portion of a shift register; Y

Figs. 2 and' 3 are charts illustrating the operation of the device ofFig. l; and

Fig. 4 is a block diagram of a shift register of n stages.

Referring to Fig. l, a portion of shift register 10 is illustrated.Included inthis portion are bistable devices i2, i4, 16. Bistable device12 consists of transistors 13, 29, which are cross coupled to form asaturation` dipilop; bistable device V 1d consists of transistors 22,24, which are cross coupled to form a second saturation iiipflop; andbistable device 16 consists of transistors 26,28, which are crosscoupled to form a third saturation ipflop.

Each of bistable devices 12, means for setting each of the dip-flops Vtoone of its two stable states and for resetting it to the other of itsstable states. Bistable device 12 is provided with set transistor 30,which is connected in parallel with transistor 1S,`and with resettransistor 32, which is connected in parallel with transistor 2f.Similarly bistable device 14 is provided with set transistor 34, whichis connected in parallel with transistor 22, and with reset transistor36, which 14, 16 is provided with y sistor 40, which is las. Y

t gates Si), 52.

Vsistor 18 to bottom.

is connected in parallel with transistor 24; and bistable device 16 isprovided with set transistor 38, which is connected in parallel withtransistor 26, and with reset 'tranconnected in Y parallel withtransistor Each of the bistable devices is associated with, or controls,a pair of conditional steering gates.' Thus bistable device 12 controlsconditional steering gates 42, 44; bistable device 14 controlsiconditional steering gates 46, 48; and bistable device 16 controlsYconditional,steering Conditional steering gate 42'consists oftransistors S4, S6, which are connectedinparallel; gate '44 consists oftransistors 58, 6i), 'which are connected in parallel; gate 46consistsof transistors 62, 64, which are connected in .parallelr gate 48consists of transistors 66, 68, which are connected in parallel; gate 50consists of transistors 79,72, which areeconnected in parallel;

d gate S2 consists of transistors 74, 76, which are conriected inparallel. e Y y Y It is possible to design circuits using pnp junctiontransistors of the alloy, grown, or surface barrier types in the commonemitter conliguration, so that the transistors of such circuits willsaturate, or bottom, if the potentials of their bases with respect totheir emitters, which are generally at ground potential, are morenegative than 0.3 v and so that the transistors will be substantially ibiased o if the potentials of their bases with respect to their emittersareapproximately 0.1 v., or more positive. These voltages obviously mayvary depending on .the characteristics of the Vtransistors used, as islwell, known in the art. In such circuits the potential of the collectorof a bottomed transistor 'will be approximately *Vf-0.1 v., or morepositive, or approximately at ground potential, which potential whenapplied to thebase of a operation of steering gates 44, 46, 48, 51352Vwill be substantially the 'saine' as that of conditional` steeringv gate42. if it is assumed initially that transistor 18 is cut oif, then thepotential of terminal 78, which is connected to the collector oftransistor 18, will be at some negative potential. rThis negativepotential, which is ,applied to the base of transistor 29, causestransistor 20 to bottom so that the potential of terminal 80, which isconnected to the collector of transistor 20, is substantially at groundpotential. The potential of terminal 78'of transistor 18 is determinedby the magnitude of the collector supply `source Vcc, which is notillustrated, and the voltage drop across load resistor S2 due to thebase currents drawn by transistor 29 and transistor S8.

When a positive pulse of suicient amplitude is applied to input terminal84 of ilip-op 12, the potential of the base of transistor 2t) will bemade more positive, raising yit approximately to ground level, whichcuts oi transistor 20. This causes the potential of collector 80 oftransistor 28 to be negative. This negative potential, which is appliedto the base of transistor 18, causes tran- Collector '78 of transistor18 becomes more positive, substantialiy reaching ground potential,lwhich is suiiicient to maintain transistor 20 cut off. The magnitude ofthe potential of terminal 80 is determinal by Vcc and the potential dropacross load resistor 86 due to the base currents drawn by transistors 18and 56. e

The application of a positive going pulse of suicient amplitude toinputterminal 88Vyvill raise the potential of is at a negative potential, thebase of transistor 56 will Yof a shift pulse.

the base of transistor 18 substantially to ground potential, Which cutso transistor 18. When transistor 18 cuts oi, the negative potential ofcollector 78 is sulicient to cause transistor 20 to bottom, and ip-op 12has returned to its initial state with transistor 1S cut off andtransistor 20 bottomed. lt should be noted that input terminals 84, 88of flip-lop 12 are directly connected to the collectors of transistors,18, 20.

Y With respect to gate 42 the base of transistor 56, which serves as oneVof the input terminals of gate 42, is connected to input terminal 88 ofdip-flop 12, and the base of transistor 54, which serves as the otherinput, terminal of gate 42, vis connected toshift terminal 98 of shiftregister 1i?. With flip-flop 12v-in its linitially defined conditionwith transistor 18 cut oit and transistor 20 bottomed, transistor 56Will also be Vcut off since its base is also substantially at groundpotential. In the absence of Ya shift pulse,'shif tterminal 90 issubstantially at ground level.l Thus the base of transistor 54 will beat ground potential and transistor'54 Will also be cut ott. Whentransistors 54, 56 are both cut off, the potential of output terminal92; which is connected to the collectors of transistors 54, S5, will beat a negative potential substantially equal to Vcc since it is connectedthrough load resistor 94. When conditional steering gate 42 is in thiscondition, it is detined as being enabled.

When a negative going shift'pulse of sucient amplitude is applied toshift terminal 98, transistor 54 bottoms. This causes the potential ofterminal 92 to increase-suddenly. This increase in potential is coupledthrough capacitor 96'to input terminal 98 of dip-flop 14 as a proper, orpositive going, pulse. If iiip-op 14 is in Y that state in which inputterminal 98 is negative, then yis in the state in which terminal 98issubstantially at ground potential, a positive going pulse applied toterminal 98 will produce no change in state of ip-op 14.

When the potential of input terminal 88 of ip-op 12 be negative andtransistor 56 will bottom. Therefore, terminal 92 will be substantiallyat ground'potential, even though transistor 54 is cut oit, because shiftterminal 9i) is substantially at ground potential in the absence Theapplication of a negative going shift pulse to terminal 90 will producesubstantially no change in the potential of terminal 92 since it wassubstantially at ground potential because of bottomed transistor 5.6.YWhen terminal 92 is substantially at ground potential, the condition of conditional steeringgate 42 is definedV as being disabled. t

As long as a shift pulse is applied to, or present at, shiftterminal 90,transistor 54 of gate 42 will remain Ybottomed, the potential of outputvterminal 92 will be maintained substantially at ground potential, andgate 42 will be disabled, irrespective of the potential of the lbase oftransistor 55. At the termination of each shift pulse, transistor 54cuts oli, releasinggate 42 to the control of flip-flop 12. The potentialof terminal 92 and the condition of gate 42 will then be determined byVwhether or not transistor 56 is bottomed or cut oi, which in turndepends upon the stateof dip-flop 12. lf input terminal 88 of ip-op 12is substantially at ground potential, then transistor 56 will also becut ofi, and the potential of terminal 92 will decrease fromsubstantially ground potential to a potential equal to Vcc, and gate 42will become enabled. This change in potential of terminal 92 is coupledas a negative going pulse by capacitor 96 to input terminal 98 offlip-flop 14. It the potential of input terminal 98 is negative, thenegative pulse will produce no change in state of flip-lop 14. If ipop14 is in that state in which terminal 98 is substantially at groundpotential, the negative pulse produced will v tive.

terminal 7S is negative may be denoted l, and the state in 4cause theimpedance between input. terminal 98r and ground through bottomedtransistor 24 is very muchv smaller than the impedance ot capacitor 96.

When a negative pulse of sutlicient amplitude is applied to the base ofset transistor 3G, ilip-iiop 12 will assume a stablel state in whichterminal 73 is substantially at ground potential. if a negative pulse ofsufficient am- ,plitude is applied to the base of reset transistor 32,ilipflop 12 will assume a stable state in which terminal 80 issubstantially at ground potential. Circuit means for applying thenecessary set and reset pulses to set transistor 36 and to resettransistor 32, respectively, of ilip-llop 12, for example, are notillustrated. Flip-hop S14-'may beset in the state in which the potentialof' terminal 162, which Y is connected to the collectors of transistors22, 34, is

substantially at ground potential, or it may be reset tov which terminal7o is at substantially ground potential may be denoted 0. The sameconvention is used to denote the states of iip-ilops 14, 16.

2 is a chart describing the permutations of the A states of hip-flops12, i4 and certain selected states of ip-ilop 16. if flip-ilops i la, 16are placed inthe states indicated in the four lines of Fig. 2, then uponthe applicaiion of a shift pulse to terminal 99, ilip-ops 12, 14, 16will have thestates indicated in the corresponding four lines ot Fig. 3.The states ofvip-ilop 16 in Fig. 2 were chosen so that ip-ilop 16 wouldchange state each time a shift pulse was applied to register 1i). ltshould also be noted that iiip-ilop "i2 does not change state when ashift pulse is applied to register 1%, since no means are illustrated toysupply signals to its input terminals Sd, SS. i

if flip-flops i2, i4, are placed in (l, O, 1 states, respectively, bythe application of negative pulses to set transistor 3@ of hip-hop 12,set transistor 34 of dip-hop 14, and reset transistor 4i) oi flip-flop16, then terminal 7S of flipofiop t2 and terminal 1&2 ot ilip-ilo'p 14,will be substantially at ground potential and terminal llal of iiipopV1o' will be at a negative potential` Gates 42, 46, 52 will bedisabled'since'transistors 55, 64, 74 will be bottomed. Gates ,df-l, 4S,E@ will be enabled since transistors 5S, 66, '72 will be cut o5. When ashift pulse is appliedY to shift terminal 9%', it is applied to thebases of transistors 54, 6G, 62, 6d, g'ta of gates '42, 44, e6, 43, Si),S2. This causes these transistors to bottom, and they remain bottomedfor the period of time the shift pulse is present at, or applied to,shift terminal 9i). in the enable gates the potentials of terminalsconnected to the collectors of the transistors, namely terminal'6 ofgate d4, terminal lofi of gate and terminal llil of gat de, increase inpotential.

The change in potential of terminal of gate 44 is coupled throughcapacitoi- 1T.2 to input terminal 1147- of flip-ildp 1.4.` Since inputterminal 114 is substantially at -ground potential, the pulse producedby enabled gate 44 upon the application of a shift pulse will produce nochange in dip-flop 14, and hip-hop 14 will remain in the O state. ofgate 48 is coupled as a positive going pulse by capacitor 116 to inputterminal 11S or" flip-hop 16. This positive going pulse causes dip-flop16 to change to its O state. If it is desired to piace a succeedinghip-flop, which is not illustrated, in the state in which hip-liep 16was prior to the application of a shift pulse, terminal 11S of gate 50will be connected by capacitor 120 to the proper int nection.

The increase in potential o' terminal 163 Y 114, causing iiip-op 14 tochange to the O state.

Vput: terminal of the succeeding, ip-op. tov causeA it' change to the lstate.

The states of flip-flops V12, 14, 16 at the termination of thershiftpulse appear in theirst line of Fig. 3. When the" shift pulseterminates, the gates arel released to the control of the iiip-iops towhich they have a D.C. con- Gates 44, 4S, 52 will become enabled, whilegates 42, 46, Sil remain disabled. The negative output pulses producedas the gates become enabled at the termination ot a shift pulse,however, do not. cause any hipiiop to change state for the reasonspointed out above. if the states of flip-hops 12, 14, 16 are not changedby setting or resetting pulses and if a second shift pulse` is appliedto register 1?, the information stored in register lil will be shiftedagain. At the termination ofthesecond pulse, ilip-ilop 16 will be in thesame state that ip-op 12 was placed in prior to the applicationoi theiirst shift pulse. The maximum number of places information may beshifted to the right in the example illustrated is. determined by thenumber of hip-flops in the register.

If ip-op 12 is placed in the 0 state, ip-op 14 in the l state, anddip-hop 16 in the 0 state by the application of the proper set and resetpulses to the proper set and reset transistors ofthe flip-hops, thentheV condition of the register is described by the second line of Fig.2. When this is the case, gates 42, 48, 50 arev disabled and gates 44,46, 52 are enabled. When a shift pulse is applied to shift terminal 9),enabledigate 44 produces a positive going pulse which is applied toinput termirl t the same time, the potential of terminal 121 which isconnected to the collectors of transistors 62, 64 becomes positivesuddenly and a positive pulse is coupled through capacitor 122 to inputterminal 124 of i'lip-op 16; this pulse causes flip-dop 16 to change tothe 1 state. The potential of terminal 126 which is connected to thecollectors of transistors 74, '76 becomes positive, and this change ofpotential may be coupled through capacitor 12S to the proper terminal ofthe succeeding flip-liep, which is not illustrated, to cause it toyassume its 0 state. The states of ilip-ops 12, 14 16 after the shiftpulse terminates are described in line 2 of Fig. 3.

lf ilip-ops 12, i4, 16 are placed in the 1, 0, 1, states, respectively,asV described in line 3 of Fig. 2, by the application of the negativegoing signal to the proper set and reset transistors of the flip-hop,then gates 44, 46, 52 will be disabled and gates 42, 48, Sil will beenabled. When a shift pulse is applied to shift terminal 90, enabledgate 42 produces a positive pulse which is applied to input terminal g8of hip-hop i4, which causes flip-op 14 to change to the 1 state. Enabledgate 48 produces a positive going pulse which is applied to inputterminal V1123 of ip-op 16, which causes flip-flop 16 to change to the4O state. Enable gate 56 also produces a pulse which could change asucceeding hip-hop, which is not illustrated, to the l state. ThestatesA of hip-hops 12, 14, 16 after the shift pulse terminates aredescribed in line 3 of Fig'. 3.

lf flip-hops 12, 14 16 are placed in the stable states l, l, 0,respectively, as indicated in line 4 of Fig. 2, then gates 44, 48, 5i)will be disabled and gates 42, 46, 52 will be enabled. If a shift pulseis applied to shift terminal 9G, enabled gate 42 will produce a positivepulse lwhich is applied to input terminal 98 of Hip-:dop 14; However,Vsince terminal 98 is substantially at ground potential, this positivepulse will cause no change of state in hip-flop 14. pulse Which causesflip-flops 16 to change to the 1 state, and enabled gate 52 produces apositive going pulse which can be used to place a succeeding flip-flopin the 0 state.

A perusal of Figs. 2 and 3 indicates that the informal tion stored inflip-flops 12, 14, prior to the application of a shift pulse, is shiftedto, or stored in, flip-ilops 14, i6

at the termination of each shift pulse. Y

Fig. 4 is a block diagram of a shift register of n stages Enabledgate'46 produces a positive with two conditional steering gates.'ofthese gates would be applied to the proper input Yterminals of theirst bistable device.

the reference numerals correspond with those whichidenftify-similar'elernents of the portion of the register illus- Vtrated in Fig. 1. From theY foregoing it is believedto be clear thatthe? number of stages which may be used'in a given shift register is amatter of choice. if it is desired to provide for end-around carry ofthe information stored lin the register, the nth bistable device may beprovided The output signals End-around carry of-the register illustratedin Fig. 1 can be achieved by connecting output terminal 110 of gate 5Gto input terfminal 88 by means of capacitor 120 and by connecting Youtput terminal 126 of gate 52 by means of capacitor t28 to inputVterminal 84 of ip-op 12.

-In the register described and illustrated, the state of Y oneflip-flophas been shifted or transferred to the next,

or succeeding, dip-flop on its right.

A register'which shifts the stored information to the left can be easily`made by connecting the output signals of the conditional steering gatesto the proper input terminals of the preceding iiip-flops. By doublingthe number of conditional steering gates per flip-dop, it is, of course,possible to form a register which will shift stored information to theright or to the left. It is also possible to cause a flip-hop of oneregister to assume a state corresponding to a state I of a flip-op Yofanother register by the use of conditional steering gates. The state ofeach nip-nop of 'a register may be determined by the potentials ofthecollectors of the transistors' of such flip-hops, as is well known inthe a'rt. Y Y

VIn an embodiment of the-invention, each of the transistors was a SBAOO,each of the resistors had a value vof substantially 680 ohms, and eachof the capacitors had a value of 470 micromicrofarads. The collectorsupply potential was substantially 3 volts. lThe values and/or types ofcomponents and the voltages are enumerated, by way of example only, asbeing suitable for the devices illustrated. It is to be understood thatcircuit specifications in accordance with the invention may vary withthe design for any particular application.

- Obviously many modilications and variations of the present inventionare'possible in the light of the above (teachings. It is, therefore, tobe understood that within i ing a rst and a second junction transistorconnected in parallel, means for applying shift pulses to the base ofVone of the transistors of said gate, circuit means for connecting thebase of the other transistor of said gate `to the collector of one ofthe transistors of the first bistable device, and a capacitor having twoterminals, one terminal of the capacitor being connected to thecollectors of the transistors of the gate and the other terminal of thecapacitor being'connected to the collector of one of "the transistors ofthe second device.

2. In combination, a iirst and a second bistable device,

' each of said devices comprising a first and a second crosscoupledjunction transistor, a first and a second conditional steering gate,each of said gates comprising a first and a second junction transistorconnected in parallel,

Va shiftV terminal adapted to have shift pulses applied thereto, circuitmeans for connecting the base of one of the transistors of the iirstgate to the collector of the second transistor of the first device,circuit means for g connecting the base of one of the transistors of thesecond gate to the collector of the first transistor of the iirstdevice, circuit means for connecting the shiftV terminal -to the'baselof vthe other transistor of each Vof said gates,

Va tirst and a second capacitor, each' oflsaidcapacitors Ahaving twoterminals, one terminal of the first capacitor being connected to thecollectors of the transistors of the iirst gate and the other terminalbeing connected to :the collector of the second transistor of the seconddevice, and loneY terminal of the second capacitor being connected-tothe collectors of the transistors of the second gate, and the otherterminal belng connected to the lcollector of the iirst transistor ofthe second device.

A 3. In-combination; n bistable ip-ops, where nis an Vinteger greaterthan l, each of said bistable nip-flops comprising a first and a secondcross-coupled transistor, the collector of the second transistor beingthe iirst input terminal of each p-op, the collector of the-iirsttranvsistor being Vthe second input terminal of each fiip-tiop,

2(n-l) conditional steering gates, each of said steer- `ing-gatescomprising two transistors connected in paral- -lel, the bases of saidtransistors serving as Vinput ter- -minals of each gate, a shiftterminal, circuit means for connecting the'base of one of thetransistors of each gate to the shift terminal, two of said gates beingcontrolled by each of (rz-'1) flip-ops, the other input terminal of therst gate controlledby each iiip-op being connected to the first inputterminal of its controlling flip-V flop, the other input terminal of thesecond gate controlled by each ip-op being connected to the second inputterminal of its controlling flip-flop, a capacitor connectingtbevcollectors of the transistors of the iirst gate controlled by eachiiip-op to the iirst input terminal of an adjacent flip-flop, and acapacitor connecting theV collectors of the transistors of the secondgate with the second input terminalof said adjacent bistable flip-op.

4. In a shift register; first and second flip-flop devices and aconditional steering-gate device, each of said devices comprising a pairof junction transistors, each of said transistors having a pair of inputcircuit electrodes `and a pair of output circuit electrodes, one of saidelectrodes being common to the input and output circuits,

each of said'flip-ilop devices includingrmeans connecting the inputcircuit electrodes of one transistor of the iiip-op across the outputcircuit electrodes of the other transistor of the iip-iiop,V said gatedevice including means connecting the output circuit electrodes of onetransistor of the gate across the output circuit electrodes of the othertransistor of the gate; means connecting the input circuit electrodes ofone transistor of the gate across the output circuit electrodes of oneof said transistors of said lirst ip-op, whereby the condition `ofsaidgate is controlled by the state of said iirst dip-flop; meansfor'connecting a source of shift pulses across the input circuitelectrodes of the other transistor of the gate for changing thecondition of said gate' if it is in one condition but 'not if it is inthe other; and a capacitor coupling the non-common output circuitelectrodes of said gate pair of transistors to the non-common inputcircuit electrode of one of the transistors of said second flip-Hop forpassing a pulse signal to said second flip-flop when and only when thecondition of said gate is changed by said shift pulse.

5. In a shift register as claimed in'claim 4 charactermon to the inputand output circuits vbeing the emitter. Y

6. In a shift register as claimed in claim 5 further characterized inthat connected in shunt with each fliptiop transistor is an additionaltransistor whose ycollector is connected to the collector of the saidflip-flop transistor and whose emitter is connected to the emitter ofthe said ip-flop transistor, said additional transistor functioning as aset or reset device.

7. In a shift register; first and second flip-Hop devices and first andsecond conditional steering-gate devices, each of said devicescomprising a pair of junction transistors, each of -said transistorshaving a pair 'of input circuit electrodes and a pair of output circuitelectrodes, one of said electrodes being common to the input and outputcircuits, each of said ip-op devices including means connecting theinput circuit electrodes of one of the transistors of the ip-op acrossthe output circuit electrodes of the other transistor of the ip- `iop,each of said gate devices including means connecting the output circuitelectrodes of both transistors of the gate in parallel; means connectingthe input cir` electrodes of bothof the other transistors of saidiirst`y and second gatesfor changing the condition of one or the otherbut not both of said gates according to the state of said, firstflip-flop; means including a first series capacitor for coupling thenon-common outputucircuit electrodes vof the pair of transistors of thefirst gate to the noncommon input circuit electrode of one of thetransistors of the second Hip-flop for passing a pulse sig-V nal to saidone transistor of said second flip-Hop when and only when the conditionof said first gate is changed by said shift pulse; and means including asecond series capacitor for coupling the non-common output circuitelectrodes of the pair of transistors of the second gate to thenon-common input circuit electrode of the other transistor of thesecondV iiip-op for passing ay pulse signal to said other transistor ofsaid second Hip-dop when and only when the condition of said second gatey is changed by said shift pulse.

8. In a shift register as claimed in claim 7 characterized in that saidinput circuit electrodes are the emitter and base, and in that saidoutput circuit electrodes vtrade of one of the 'transistors of thefliplfi'op 'nextadjacent to said-associated flip-nop for passing a pulsesignal to said next Hip-flop when and only when the condition of saidiirst gate 'is changed by said shift pulse; and means including asecondseries capacitor for coupling the output circuit' electrodes of thetransistors of each second gate to the non-common input circuitelectrode of the other transistor of said next iiip-op for passing apulse signal to said next ip-flop'when and only when the condition ofsaid second gate is changed by said shift pulse.l

l0.l In a shift register as claimed in claim '9 characterized in thatsaid input circuit electrodes are the base and emitter and in that saidoutput circuit electrodes are the collector and emitter, said electrodewhich is common to the input and output circuits being the emitter.

il. In a shift register as claimed in claimV l0 further 'characterizedin that connected inY shunt with each iiipop transistor is anadditional. transistor Whose Vcollector is connected to the collector ofthe said dip-flop p transistor and whose emitter is connected to theemitter of the said flip-flop transistor, said additional transistorfunctioning as' a set or reset device.

l2. Ina shift register; a plurality of nip-flops and a` plurality ofconditional steering gates, there being a iirst and second conditionalsteering gate associated l with each ip-op, each of said nip-flops andsteering gates comprising a pair of semi-conductor switches,l each ofsaid switches having a pair of input circuit terminals and a pair ofoutput circuit terminals, each of said nipops including means connectingthe input circuit terminals of one of the switches of the iiip--opacross the output circuit terminals of the other switch of the flipiiop,each of said gates including means for connecting the output circuitterminals of both switches of the gate in parallel; means connecting theinput circuit V- terminals of one switch of each first gate across theoutare the collector and emitter, said electrode which is t of one o'fthe transistors of the dip-dop across the output circuit electrodes ofthe other transistor of the iiip-op, each of said gates including meansfor connecting'in parallel the output circuit electrodes of bothtransistors of the gate; means connecting the input circuit electrodesof one transistor of each rst gate across the output circuit electrodesof one of the transistors of the associated iiip-op, whereby thecondition of each first gate is controlled by the state of itsassociated hip-flop; means connecting the input circuit electrodesfofone transistor of each second gate across the output circuit electrodesof the other transistor of the associated iiipfiop, whereby thecondition of each second gate isoppositely controlled by the state ofsaid associated ip-op; means for connecting a source of shift pulsesacross the input circuit electrodes of both of the other transistors ofeach irst and second gates for changing the condition of one or theother but not both of said gates according to the state of theassociated ip-op; means including a rst series capacitor for couplingthe non-common output circuit electrodes of the pair of transistors ofeach first gate to the non-common input circuit elecputcircuit'terminals of one of the switches of the associated ip-op,whereby the condition of each rst gate is controlled by the state ofsaid associated flip-nop; means connecting the input circuit terminalsof one switch of each second gate across the output circuit terminals ofthe other switch of the associated flip-nop, whereby the condition ofeach second gate is oppositely controlled by the state of saidassociated flip-flop; means for connecting a source of shift pulsesacross the input circuit terminals of both of the other switches of eachsaid Virst and second gates for changing the condition of one or theother but not both of said gates according to the state of' theassociated Hip-Hop; means including a first series capacitor forcoupling the output circuit terminals of the pair of switches of eachfirst gate across the input circuit terminals of one of the switches ofeach of each second gate across the input circuit terminals of vtheother switch of said next iiip-op for passing a pulse signal to saidnext ip-iiop when and lonly when the condition of said second gate ischanged by said shift pulse.

13. In a shift register as claimed in claim 8 further characterized inthat connected in shunt with each iiipflop transistor is an additionaltransistor whose collector is connected to the collector of thesaid-'flip-op transistor and Whosefemitter is connected to the emitterof the said iiip-op transistor, said additional transistor functioningas a set or reset device.

14. In combination; a plurality of Hip-ops and a plurality ofconditional steering gates, there being rst and second gates associatedwith each dip-flop, each of said flip-Hops and each of said gatescomprising a pair -of junction't'ransisto'rs, each of said transistors:havinga Apair' of input circuit electrodes and a pair of output cir-.cuit' electrodes, one of said electrodes being common to 'the input andoutput circuits, each of said dip-flops Vincluding means connecting 'theinput circuit electrodesk of one of the transistors of the iiip-opacross thel output kcircuit electrodes of the othertransistor of theip-lop, each of said gates including means for connecting in parallelthe output circuit electrodes of both transistors vot' the gate; meansconnecting the input circuit electrodes of one transistor of each firstgate across the output circuit electrodes ofone of the transistors ofthe associated iiip-op, whereby the condition of each iirst gate A iscontrolled by the state of its associated ip-op; means yfor connecting asource kot' shift pulses across theinput circuit electrodes of both ofthe other transistorsY of each rst and second gates for changing thecondition of one or the other but not bothlofY said `gates according tothe state of the associated flip-flop; means including a iirst seriescapacitor for Ycoupling the non-common output circuit electrodes of thepair of transistors of each rst gate to the non-common input circuitelectrode of ,one of the transistors of a ip-op other than saidassociated flip-op for passing a pulse signal to said other ip-op whenand only when the condition of said rst gate is changed by said shiftpulse; and means including a second series capacitor for coupling theinput circuit electrodes of the transistors of each second gate to the12 non-common input circuit velectrode of the other tran sistor ofsaidr'other ip-tiop 'for' passing a pulse signal to said other ilip-opwhen and only whenthe condition of said second gate is changed by saidshift pulse.

15. Apparatus as clairned` in-clairn 14 characterized in that said inputcircuit electrodes are the base and emitter and in that saidoutput'circuit electrodes are the collector and'ernitter, said electrodewhich is common to the input and output circuits being the emitter.

16. Apparatus as claimed in claim 15 further characterized in thatconnected in shunt with each ip-op transistor is an additionaltransistor whose collector is connected to the collector of the'saiddip-flop transistor and whose emitter is connected to the emitter of thesaid ip-op transistor, said additional transistor yfunctioning as a setor reset device. Y

References Cited-in the tile of this patent 'Y UNITED STATES APArENTs2,404,047 Flory et al. L YJuly 16, 1946 2,409,689 Morton et al. Oct. 22,1946 2,445,215 Flory a July 13, 1948 2,580,771 Harper Ian. 1, 19522,715,678 BarneyV Aug. 16, 1955 2,764,343 Diener Sept. 25, 19562,785,304 Bruce et al. Mar. 12, 1957 2,808,203 Geyer'et al Oct. 1, 1957OTHER REFERENCES Coupled Transistor Circuits, by R. H. Beter et al.(Fig. 7 at page 135v relied'on.)

